1. Field of the Invention
The present invention relates to a monitor pattern of a semiconductor device, which detects abnormality of wiring (including a contact portion) occurring in manufacturing steps of the semiconductor device, and to a method of manufacturing the semiconductor device.
2. Description of the Prior Art
In recent years, along with miniaturization of a semiconductor device, demand for a system LSI has been growing. In the system LSI, because of a great difference in wiring density between a portion where the wiring is not dense and a portion where the wiring is dense, manufacturing conditions are not even between the two portions. Thus, thinning of the wiring, contact failure, disconnection, short-circuiting and the like are likely to occur. Accordingly, an electrically isolated dummy pattern is provided in the portion where the wiring is not dense, thus setting a pattern density in a constant range.
Moreover, in some cases, a monitor pattern is previously provided in a semiconductor substrate (a wafer). The monitor pattern is formed simultaneously with normal wiring and is used in order to electrically examine whether or not a pattern width exceeds its allowable range and whether or not a contact is normal.
FIG. 1A is a top plan view showing an example of a monitor pattern provided in a conventional semiconductor device, and FIG. 1B is a cross-section view thereof.
On a semiconductor substrate 10, an impurity diffusion layer (not shown) constituting elements such as a transistor and the like is formed, and a plurality of wiring layers are formed thereon while sandwiching an interlayer insulation film therebetween. An impurity diffusion region and wirings of the respective wiring layers are connected via contact vias buried in the interlayer insulation film, and thus a predetermined circuit is constituted.
As shown in FIGS. 1A and 1B, the monitor pattern is constituted by: a plurality of lower-layer wirings 11 formed in line on a first interlayer insulation film (not shown); a plurality of upper-layer wirings 14 formed in line on a second interlayer insulation film 12; and contact vias 13 buried in the second interlayer insulation film 12. The respective lower-layer wirings 11 electrically connect the upper-layer wirings 14, which are mutually adjacent with each other via the contact vias 13.
In general, widths of the lower-layer wiring 11 and of the upper-layer wiring 14 are set to be minimum line widths decided on design criteria. For example, as a monitor pattern, one having the lower-layer wiring 11 and upper-layer wiring 14, which are 0.3 fÊm in width, 0.9 fÊm in length and having the contact vias 13 of which number is set to 100 is currently used.
FIG. 2 is a top plan view showing another example of the conventional monitor pattern. This monitor pattern 16 is constituted by one wiring, which is bent repeatedly. A width of the wiring is set to a minimum line width decided on the design criteria. Conventionally, as a monitor pattern of this kind, for example, one is used, in which the width of the wiring is set to 0.3 fÊm and a length (a total length) thereof is set to 100 fÊm.
The monitor patterns described above are formed on a scribe line of the wafer, that is, in a region between chip formation portions. Electrical characteristics (such as a resistance value and the like) of the monitor pattern are measured by a detection device. When the electrical characteristics are within a predetermined range, a manufacturing condition can be determined to be appropriate. On the other hand, when the electrical characteristics of the monitor pattern are out of the predetermined range, there is a high possibility that problems occur such as thinning of the wiring, contact failure, short-circuiting, disconnection and the like.
However, the inventors of the present application and the like consider that the conventional monitor pattern described above has a problem described below.
FIG. 3A is a graph showing a relationship between a pattern occupying ratio, which is indicated by a horizontal axis, and a frequency of constrictions generated in a wiring, which is indicated by a vertical axis. In the case where a space between a wiring and a peripheral wiring of it is large (large space), even if the pattern occupying ratio is small, the constriction is not generated. However, in the case where the space between a wiring and a peripheral wiring of it is small (small space), when the pattern occupying ratio is small, a constriction (an undercut) 23 of a wiring as shown in FIG. 3B is generated. Note that, in FIG. 3B, reference numeral 21 indicates a barrier metal and reference numeral 22 indicates an Al (aluminum) wiring.
The above problem can be conceived as below. Specifically, when a wiring is formed by dry etching, an organic substance (an organic substance released from a resist film) covers a sidewall of the wiring, as the etching is performed, and protects the wiring from an etching gas. Particularly, in the case of using Al (aluminum) as a wiring material, since Al is apt to react to Cl (chlorine) in the etching gas, it is necessary to cover the entire sidewall of the wiring 22 with the organic substance.
However, when the pattern occupying ratio (a wiring occupying area) is small, an amount of the organic substance supplied from the resist film is relatively decreased. Thus, it becomes impossible to cover a lower portion of the Al wiring 22 with the organic substance. As a result, as shown in FIG. 3B, the constriction 23 is generated in the lower portion of the Al wiring 22.
Because the monitor pattern is formed in a place away from the chip formation portion, such as on the scribe line, a space between the monitor pattern and other patterns is large, thus making it difficult for the constriction to be generated. On the other hand, in the chip formation portion, the space therebetween is small, and thus the constriction is likely to be generated. Therefore, even if no abnormality is detected by the electrical examination of the monitor pattern, it cannot be completely said that there is no abnormality in the wiring in the chip formation portion.
FIGS. 4A and 4B are top plan views showing examples of patterns, respectively, in which failure is likely to occur. FIGS. 4C and 4D are perspective views thereof, respectively. As shown in the drawings, as for patterns 31a and 31b surrounded by other patterns 32a and 32b, respectively, in circled portions the constriction is likely to be generated, the constriction being dependent on the pattern occupying ratio, as shown in FIG. 3B.
A wiring structure which is considered most likely to lead to failure includes, as shown in FIG. 5, a portion where a lower-layer wiring (Al wiring) 42 and an upper-layer wiring (Al wiring) 46 are connected by use of a contact via 44. Usually, a barrier metal 41 is formed below the lower-layer wiring 42, and a reflection preventing film (for example, a TiN film) 43 is formed thereon. Moreover, a barrier metal 45 is also formed below the upper-layer wiring 46, and a reflection preventing film 47 is formed thereon. In such portions, constrictions are generated in an upper portion of the lower-layer wiring 42 (below the reflection preventing film 43) and in a lower portion of the upper-layer wiring 46 (above the barrier metal 45). Accordingly, contact resistance between the lower-layer wiring 42 and the upper-layer wiring 46 is increased, thus leading to a defective product in extreme cases.
However, as described above, the electrical examination by use of the conventional monitor pattern may not be able to detect abnormality of the wiring in the chip formation portion. Thus, necessity of cross-section observation and the like arises in order to identify the cause of the failure. Therefore, a lot time is required to examine the cause and take measures therefore, resulting in a delay of a feedback into manufacturing steps.